`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:23:46 12/01/2010 
// Design Name: 
// Module Name:    vga_matrix 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module vga_matrix(vidon, vc, hc, red, green, blue);

input wire vidon;
input wire [9:0] vc, hc;
output reg [2:0] red, green;
output reg [1:0] blue;

reg display_buffer [79:0][59:0];
reg [8:0] i,j;
wire c;

always @ (*)
begin
	
	pinta U1(.x(hc[9:3]), .y(vc[9:3]), .clk(vidon), .c(c));
	
	if (vidon) begin
		red = {c,c,c};
		green = {c,c,c};
		blue = {c,c};
	end
end

endmodule
